The present invention relates to a method and a structure for reducing the effects of buckling in fabricating semiconductor wafers.
One pronounced goal in the semiconductor industry is high device yields. To achieve this end, it is essential to employ a flat semiconductor wafer. If the process steps involved in semiconductor fabrication are performed on a non-uniform wafer surface, various problems may arise resulting in a substantial number of inoperable devices and, thus, a low yield.
Previous methods used to ensure the wafer surface planarity have included forming an oxide such as BoroPhosphoSilicate Glass (xe2x80x9cBPSGxe2x80x9d) layer on the wafer surface. These methods have then employed a heating step, as applied to the wafer, to reflow and planarize the oxide layer. However, this xe2x80x9creflowxe2x80x9d method of planarizing the wafer surface is substantially limited in light of large device geometries and thermal budgets because of the buckling, also referred to as cracking or wrinkling, of multilayer heterostructures
Buckling of layers in the manufacture of semiconductor wafers pertains to the relationship between a heterostructures disposed upon each other. This relationship is depicted in FIG. 1 where a first layer 10, comprising a semiconductor substrate for example, is illustrated having a second layer 20 positioned superjacent. Unfortunately, first layer 10 and second layer 20 both have different thermal expansion coefficients. As such, first layer 10 expands at a rate inherent to the characteristics of its chemical composition during reflow, while the second layer, comprising a different chemical composition than the first layer, expands at an entirely different rate.
This buckling effect is illustrated in FIGS. 2 and 3. FIG. 2 provides a cross-sectional perspective of a buckled semiconductor substrate. FIG. 3 depicts a top view of a buckled semiconductor substrate as obtained using Atomic Forced Microscopy (AFM). In view of both Figures, the distance between a high point and low point is on the order of one micron. With the top surface of the substrate distorted by the effects of buckling, later stages in the fabrication process of the semiconductor device are substantially impacted. For example, during a subsequent etch, an implanted dopant positioned underneath the low point of the distortion may be unintentionally removed or inadvertently allowed to interact with other compounds.
Another method which has been used to produce a planar wafer surface is to use the oxide reflow method described above, in conjunction with spin coating the wafer with photoresist. The spin coating fills the low points on the wafer surface, thereby producing a planar surface. Next, a dry etch, which removes photoresist and oxide at a rate sufficiently close to 1:1, etches the photoresist and the high points on the wafer surface, thereby producing a planar oxide layer on the wafer surface.
Irrespective of either method for providing a planar surface, the buckling of layers still develops during the step of reflow because of the materials employed and their different thermal expansion coefficients. As such, with technology enabling the development of smaller and smaller device feature sizes, a new process is needed to circumvent the debilitating effects of buckling.
One object of the present invention is to provide a method for reducing the effects of buckling in fabricating a semiconductor wafer.
A further object of the present invention is to provide a semiconductor device impervious to the effects of buckling.
Still another object of the present invention is to provide a method which enables a uniform reflow of layers involved in the fabrication of semiconductors.
Yet another object of the present invention is to provide a semiconductor device which allows for the uniform reflow of layers in the fabrication of the device.
Another object of the present invention is to activate or modify the characteristics of a layer as a function of thermal budget and chemical reaction.
In order to achieve the hereinabove objects, as well as others which will become apparent hereafter, a method is disclosed for reducing the effects of buckling, also referred to as cracking or wrinkling in multilayer heterostructures. The first step of the present method involves forming a planarization layer superjacent a semiconductor substrate. The planarization layer comprises tungsten, titanium, tantalum, copper, aluminum, single crystal silicon, polycrystalline silicon, amorphous silicon, borophosphosilicate glass (xe2x80x9cBPSGxe2x80x9d) or tetraethylorthosilicate, (xe2x80x9cTEOSxe2x80x9d). Next, a barrier film having a structural integrity is formed superjacent said planarization layer by exposing said substrate to a gas and radiant energy. The gas comprises a reactive or inert gas or mixture thereof, including at least one of N2, NH3, O2, N2O, Ar, Arxe2x80x94H2, H2, GeH4, and a Fluorine based gas, while the radiant energy generates heat within the range of 500xc2x0 C. to 1250xc2x0 C. Subsequently, a second layer is formed superjacent the barrier film. The second layer comprises tungsten, titanium, tantalum, copper, aluminum, single crystal silicon, polycrystalline silicon, amorphous silicon, borophosphosilicate glass (xe2x80x9cBPSGxe2x80x9d) or tetraethylorthosilicate (xe2x80x9cTEOSxe2x80x9d). Finally, the substrate is heated a temperature in the range of 700xc2x0 C. to cause the planarization layer to expand according to a first thermal coefficient of expansion, the second layer to expand according to a second thermal coefficient of expansion, and the structural integrity of the barrier film to be maintained. This results in the barrier film isolating the planarization layer from the second layer, thereby preventing the planarization layer and the second layer from interacting during the heating step. Further, it enables the planarization layer to go through a solid state reaction and the second layer to obtain a uniform reflow.
Moreover, in order to achieve additional objects, a semiconductor device resistant to the effects of buckling is disclosed. The device comprises a first layer superjacent a semiconductor substrate and a barrier film positioned superjacent the substrate having a structural integrity. The first layer comprises tungsten, titanium, tantalum, copper, aluminum, single crystal silicon, polycrystalline silicon, amorphous silicon, borophosphosilicate glass (xe2x80x9cBPSGxe2x80x9d) or tetraethylorthosilicate (xe2x80x9cTEOSxe2x80x9d). Furthermore, the barrier layer comprises titanium nitride, tantalum nitride, titanium oxide, tantalum oxide, silicon dioxide, silicon nitride or tetraethylorthosilicate (xe2x80x9cTEOSxe2x80x9d). Moreover, a second layer is positioned superjacent the barrier film, the second layer comprising tungsten, titanium, tantalum, copper, aluminum, single crystal silicon, polycrystalline silicon, amorphous silicon, borophosphosilicate glass (xe2x80x9cBPSGxe2x80x9d) or tetraethylorthosilicate (xe2x80x9cTEOSxe2x80x9d). By employing the barrier film between the first and second layers, both first and second layers are isolated from each other when a temperature of at least 700xc2x0 C. is applied, thereby preventing any interaction between the first layer and the second layer. This configuration additionally enables the first layer and the second layer to uniformly reflow during a heating step.
Other objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.